The present invention relates to a semiconductor memory device having a redundancy repair circuit.
In general, a semiconductor memory device such as a static random access memory (SRAM) and a dynamic random access memory (DRAM) places an auxiliary memory cell array in addition to a regular memory cell array in order to improve its yield. When it is determined that a defective memory cell exists in the regular memory cell array in the testing process of the semiconductor memory device, the defective memory cell is replaced with the auxiliary memory cell, thereby to complete the semiconductor memory device as a non-defective unit. That is, so-called redundancy repair is performed.
The technology of a prior art semiconductor memory device will be explained below.
FIG. 7 is a configuration view of the prior art semiconductor memory device (SRAM). The semiconductor memory device in FIG. 7 has memory cells 1, word-line drivers 2, a redundant word-line driver 3, a bit-line precharge control signal line driver 4, bit-line precharge circuits 5, word lines WL1 and WL2, a redundant word-line RWL, pairs of bit lines BL1, /BL1 and BL2, /BL2, and a bit-line precharge control signal line PCGL.
WLCG1 to WLCG 3 and PCG designate word-line control signals and a bit-line precharge control signal, respectively, and mark A indicates a break in the word line.
The word-line drivers 2 are buffers connected to the respective word lines WL1, WL2 and transmit the respective word-line control signals WLCG1, WLCG2 inputted to each memory cell 1 through the respective word lines WL1, WL2.
The redundant word-line driver 3 is a buffer connected to the redundant word-line RWL, and in the case where a defect exists in the word line WL1 or WL2, the driver 3 transmits the inputted word-line control signal WLCG3 to each memory cell 1 through the redundant word-line RWL.
The bit-line precharge control signal line driver 4 is a buffer connected to the bit-line precharge control signal line PCGL, outputs the inputted bit-line precharge control signal PCG to the bit-line precharge control signal line PCGL and activates or deactivates the bit-line precharge circuits 5.
Each memory cell 1 is connected to a word line (including a redundant word line) and a pair of bit lines.
FIG. 8 is a circuit diagram showing the specific configuration of the memory cell 1. In FIG. 8, Q1 and Q2 are access transistors, Q3 and Q4 are drive transistors, Q5 and Q6 are load transistors, WL is a word line, BL and /BL are a pair of bit lines, and VDD is a power source terminal.
Gate terminals of the access transistors Q1 and Q2 are connected to the word line WL or the redundant word line RWL and drain terminals thereof are connected to the pair of bit lines BL and /BL, respectively.
The drive transistor Q3 and the load transistor Q5 form a first inverter and the drive transistor Q4 and the load transistor Q6 form a second inverter.
An output terminal of the first inverter is connected to an input terminal of the second inverter and an output terminal of the second inverter is connected to an input terminal of the first inverter so that a latch circuit is constituted. The latch circuit stores and holds data. When the word line WL or redundant word line RWL becomes H level, the memory cells 1 connected to the line output data stored therein to the pair of bit lines BL and /BL or receive complementary signals (data) transmitted through the pairs of bit lines BL and /BL.
FIG. 9 is a circuit diagram showing the specific configuration of the bit-line precharge circuit 5. In FIG. 9, Q7 and Q8 are precharge transistors, Q9 is an equalize transistor, BL and /BL are a pair of bit lines, PCGL is a bit-line precharge control signal line, and VDD is a power source terminal.
Each gate terminal of the precharge transistors Q7, Q8 and the equalize transistor Q9 are connected to the bit-line precharge control signal line PCGL and receives input of the bit-line precharge control signal. Drain terminals of the precharge transistors Q7 and Q8 are connected to the pair of bit lines BL and /BL, respectively and source terminals are connected to the power source terminal VDD. The source terminal and drain terminal of the equalize transistor Q9 are connected to the pair of bit lines BL and /BL, respectively.
When the bit-line precharge control signal PCG is L level, the bit-line precharge circuit 5 becomes activated and precharges pairs of bit lines BL1, /BL and BL2, /BL2. When the bit-line precharge control signal PCG is H level, the bit-line precharge circuit 5 becomes deactivated and goes into a high impedance state.
Operations of the semiconductor memory device thus constituted will be described below. Firstly, the case where no break A occurs in the word line will be explained.
When all of the word-line drivers 2 and the redundant word-line driver 3 output the word-line control signals WLCG1 to WLCG3 of L level, all memory cells 1 go into a high impedance state (the state in which data input/output is not performed). At that time, the bit-line precharge control signal PCG (output signal of the bit-line precharge control signal line driver 4) becomes L level and the bit-line precharge circuit 5 goes into an activated state. All pairs of bit lines BL and /BL are precharged to H level (VDD level) by the bit-line precharge circuits 5.
Next, when the bit-line precharge control signal PCG becomes H level, the bit-line precharge circuits 5 go into a deactivated state (high-impedance state).
When any one of all of the word-line drivers 2 and the redundant word-line driver 3 outputs H level, the memory cell 1 to which H level is inputted through the word line WL or RWL becomes activated (writing or reading of data is carried out). In the memory cell 1 which receives input of the word-line control signal WLCG of H level, gates of the access transistors Q1 and Q2 turns ON and writing or reading data to/from the latch circuit Q3 to Q6 is performed through the pair of bit lines BL and /BL connected to the access transistors Q1 and Q2, respectively.
When writing or reading data to/from the memory cell 1 is completed, the word-line control signal WLCG returns to L level from H level and the memory cell 1 goes into a high impedance state. The bit-line precharge control signal PCG becomes L level again and the bit-line precharge circuits 5 are activated, so that the pairs of bit lines BL and /BL are precharged to H level. Subsequently, the above-mentioned processing is repeated.
Next, the case where a break A occurs in the word line will be explained.
Suppose that a break occurs at the point indicated as A in FIG. 7. Even if the word-line driver 2 transmits the word-line control signal of H level through the word line WL1 with the break, it is impossible to properly write and read data to/from the memory cell connected to the word line WL1 on the right side from the break point A.
In such a case, by performing redundancy repair generally according to the below-mentioned method, a non-defective semiconductor memory device is achieved. The word line WL1 with the break is made to L level (the input terminal of the word line driver 2 connected to the word-line WL1 is grounded) and all memory cells 1 connected to the word line WL1 are made to be in a high impedance state. The word-line control signal WLCG which were inputted to the word-line driver 2 of the word line WL1 if it were not for the break is inputted to the redundant word-line driver 3. The redundant word-line driver 3 transmits the word-line control signal WLCG to the memory cells 1 through the redundant word line RWL, whereby that writing or reading data is performed in the memory cells 1 connected to the redundant word line RWL. By replacing the memory cells 1 connected to the word line WL1 having the break with the memory cells 1 connected to the redundant word line RWL, the semiconductor memory device can perform proper writing and reading of data.
However, the above-mentioned conventional configuration has problems as stated below.
In FIG. 7, even if an input terminal of the word-line driver 2 connected to the word line WL1 with the break is ground level, the word line WL1 on the right side from the break point A remains in a floating state. In the case where the potential of the word line WL1 in a floating state equals the gate threshold of the access transistors Q1 and Q2 of the memory cell 1 or greater, all the memory cell 1 connected to the word line on the right side from the break point A is always in an activated state (the state in which writing or reading of data is always performed at all times).
Even if the memory cells connected to the word line WL1 with the break are replaced with memory cells connected to the redundant word line RWL, there is a possibility that the memory cell 1 connected to the word line in a floating state remains activated in the memory cell array. In the case where normal word lines other than the word line WL1 with the break (the word line WL2 and the redundant word line RWL in FIG. 7) become H level, data conflict between the memory cells 1 which are connected to the word line WL1 in a floating state and remain activated and the memory cells 1 which are connected to the normal word line and become activated according to the word-line control signal may occur through the pair of bit lines (BL2 and /BL2 in FIG. 7), resulting in damaging data of memory cells 1 connected to the normal word line.
Further, during the period when the bit-line precharge control signal PCG becomes L level and the pairs of bit lines are precharged to H level, the problem arises that a pass-through current flows between the memory cell connected to the word line in a floating state-and the bit-line precharge circuit. The above-mentioned example is the case where the break occurs in the word line, the same problem also arises when the break occurs in the redundant word line.
The present invention solves the above-mentioned conventional problems and object thereof is to provide a semiconductor memory device capable of performing redundancy repair of defect in the word line due to break more securely.
A semiconductor memory device according to the present invention from one aspect comprises plural word lines including one or more redundant word lines, plural pairs of bit lines, plural memory cells connected to the plural word lines and the plural pairs of bit lines, plural word-line drivers which are connected to one ends of the plural word lines and controlled by plural word-line control signals respectively, and plural word-line control elements which are connected to other ends of the plural word lines and controlled by a control signal activated at the precharge of the bit lines.
In the above-mentioned semiconductor memory device according to the present invention from another aspect, the plural word-line control elements are controlled by a precharge control signal and a redundant selection signal.
In the above-mentioned semiconductor memory device according to the present invention from another aspect, the plural word-line control elements are formed by using elements of dummy memory cells disposed on the periphery of a memory cell array which consists of the plural memory cells.
A semiconductor memory device according to the present invention from another aspect comprises plural word lines including one or more redundant word lines, plural pairs of bit lines, plural memory cells connected to the plural word lines and the plural pairs of bit lines, plural word-line drivers which are connected to one ends of the plural word lines and controlled by plural word-line control signals respectively, plural first word-line control elements which are connected to other ends of the plural word lines respectively and controlled by a control signal activated at the precharge of said bit lines, and plural second word-line control elements which are connected to any points other than both ends of said plural word lines and controlled by a control signal activated at the precharge of the bit lines.
In the above-mentioned semiconductor memory device according to the present invention from another aspect, the plural first word-line control elements and the plural second word-line control elements are controlled by a precharge control signal and a redundant selection signal.
In the above-mentioned semiconductor memory device according to the present invention from another aspect, the plural first word-line control elements and the plural second word-line control elements are formed by using elements of dummy memory cells disposed on the periphery of a memory cell array which consists of the plural memory cells.
With the above-mentioned configuration, in the semiconductor memory device, the word-line control elements which are controlled by a control signal activated at the precharge of bit lines are connected to the far ends of all word lines including the redundant word line (the end opposite to connecting end with the word-line driver, the other end). The word-line control element causes all word lines to be the level in which the memory cell becomes a deactivated state during the precharge period of the pair of bit lines. The word-line control element becomes high-impedance state during the period other than the precharge period of the pair of bit lines. Accordingly, data conflict between the memory cells connected to the word line with the break defect and the memory cells connected to the normal word line via the pair of bit lines is prevented from occurring, and a pass-through current is prevented from flowing between the memory cell connected to the word line in which the break defect occurs and the bit-line precharge circuit during the period when the pair of bit lines are precharged. This enables to securely repair defect of word line due to break in the semiconductor memory device by using redundancy method.
In the semiconductor memory device according to an additional aspect of the present invention, in the absence of break defect in the word line, change in the bit-line precharge control reverse signal is eliminated by controlling the word-line control element with the redundant selection signal. This prevents flow of any charging and discharging current of the bit-line precharge control reverse signal, thereby achieving lower power consumption in the semiconductor memory device.
Further, it is possible to suppress increase in layout area of the semiconductor memory device by constituting the word-line control element with the dummy memory cell. Preferably, by means of only modification of aluminum wiring without changing pattern of semiconductor substrate, the element of the dummy memory cell is used as the bit-line control element. This causes no bad influence in processing the shape of the memory cell array when the element of the dummy memory cell is transformed to the bit-line control element.
Furthermore, the word-line control element which is controlled by the control signal activated at the precharge of the bit lines is connected to far ends (the end opposite to the connecting end with the word-line driver, other end) and any points other than the far ends of all word lines including the redundant word line. Thereby, data conflict between the memory cell connected to a word line with the break defect at plural points and the memory cell connected to the normal word line via the pair of bit lines is prevented from occurring, and a pass-through current between the memory cell connected to the word line in which the break defect at plural points and the bit-line precharge circuit is prevented from flowing during the period when the pair of bit lines are precharged. This enables to improve the probability of being able to repair defect of word line due to break in the semiconductor memory device.
Furthermore, in the absence of break defect in the word line, change in the bit-line precharge control reverse signal is eliminated by controlling the word-line control element with the redundant selection signal. This prevents flow of any charging and discharging current of the bit-line precharge control reverse signal, thereby achieving lower power consumption in the semiconductor memory device.
Furthermore, it is possible to suppress increase in layout area of the semiconductor memory device by constituting the word-line control element with the dummy memory cell.
The novel features of the invention are set forth with particularity in the appended claims. The invention as to both structure and content, and other objects and features thereof will best be understood from the detailed description when considered in connection with the accompanying drawings.